Direct wafer bonding for MEMS and microelectronics

Direct wafer bonding is a method for fabricating advanced substrates for microelectromechanical systems (MEMS) and integrated circuits (IC). The most typical example of such an advanced substrate is the silicon-on-insulator (SOI) wafer. SOI wafers offer many advantages over conventional silicon wafers. In IC technology, the switching speed of circuits fabricated on SOI is increased by 20-50% compared to circuits fabricated on a bulk Si wafer. The required operation voltage is lower in ICs on SOI than in ICs on a bulk silicon wafer, which decreases power consumption and chip heating. In the MEMS industry, the buried oxide layer works as a good sacrificial layer during release etching of diaphragms, beams etc. and offers an excellent etch stop layer for silicon etching. Direct wafer bonding can also be used in the fabrication of more complex structures than SOI. The wafers to be bonded can be of different materials, can contain patterns, and may have multiple layers or ready-made devices. This thesis reports on studies of direct wafer bonding and its use in various applications. Different bonding processes used in microelectronics are briefly described. The main focus of this thesis is on the plasma activation-based low temperature bonding process, and on the control of bond strength by surface preparation. A novel method for bond strength measurement is introduced. This method, based on buried oxide etching, is presented and compared with other methods used in evaluating bond quality. This thesis also contains results on research of different applications requiring direct wafer bonding. Heterogeneous integration, pre-processed SOI fabrication, and wafer scale packaging are the main application topics.